IBM reveals nanostack transistor design targeting sub-1nm performance

A fresh chip design unveiled by IBM reportedly packs nearly 100 billion transistors onto a surface no larger than a human fingernail, almost doubling the density achieved in the firm’s last generation of technology. The company positions the advance as the “world’s first sub-1 nanometer chip technology” developed specifically for AI data centers.

Vertical stacking overcomes physical limits. The nanostack approach places transistors atop one another in an offset pattern, allowing far more of them to occupy the same area. It extends the nanosheet devices that first appeared in IBM’s 2-nanometer process launched in 2021.

At its core, the architecture bonds two transistors together vertically. Each transistor contains three nanosheets measuring 5 nanometers thick—roughly 15 rows of silicon atoms—with approximately 9 nanometers between neighboring sheets.

Projected gains aim at AI-era demands. Technical papers released by the company forecast that the new layout can deliver 50 percent higher computing performance or 70 percent greater energy efficiency relative to its 2-nanometer predecessor. IBM first presented the nanostack concept at the 2025 IEEE Symposium on VLSI Technology and Circuits held in Kyoto, Japan.

Separate work shown at the VLSI 2026 symposium indicated a 40 percent scaling improvement for SRAM. The gain stems from a staggered-channel layout inside SRAM bit cells—each built from six transistors—that shrinks cell height by 40 percent and fits more memory in the same footprint.

SRAM density boost addresses AI needs. That extra memory capacity matters because SRAM handles rapid yet power-hungry read and write cycles required by many AI tasks. The improvement arrives after SRAM scaling has slowed sharply; the step from 3-nanometer to 2-nanometer processes delivered only a few percent density gain.

Node labels no longer reflect true size. IBM calls the technology a 0.7-nanometer or 7 angstrom node, even though modern process names have long since decoupled from actual physical dimensions. Feature sizes stopped matching node numbers after the 180-nanometer era of the 1970s and 1980s.

“It’s not just an incremental step, it’s a meaningful leap forward,” said Jay Gambetta, director of IBM Research and IBM Fellow. He added that the platform “pointing to a future where computing becomes significantly more powerful without a corresponding increase in energy.”